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LT8300 1 8300f typical a pplica t ion fea t ures descrip t ion 100v in micropower isolated flyback converter with 150v/260ma switch the lt ? 8300 is a micropower high voltage isolated flyback converter. by sampling the isolated output voltage directly from the primary-side flyback waveform, the part requires no third winding or opto-isolator for regulation. the output voltage is programmed with a single external resistor. in - ternal compensation and soft-start further reduce external component count. boundary mode operation provides a small magnetic solution with excellent load regulation. low ripple burst mode operation maintains high efficiency at light load while minimizing the output voltage ripple. a 260ma, 150v dmos power switch is integrated along with all high voltage circuitry and control logic into a 5-lead thinsot? package. the LT8300 operates from an input voltages range of 6v to 100v and can deliver up to 2w of isolated output power. the high level of integration and the use of boundary and low ripple burst modes result in a simple to use, low component count, and high efficiency application solution for isolated power delivery. l , lt, ltc, ltm, linear technology, the linear logo and burst mode are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5438499, 7463497, and 7471522. 5v micropower isolated flyback converter a pplica t ions n 6v to 100v input voltage range n 260ma, 150v internal dmos power switch n low quiescent current: 70a in sleep mode 330a in active mode n boundary mode operation at heavy load n low-ripple burst mode ? operation at light load n minimum load <0.5% (typ) of full output n v out set with a single external resistor n no transformer third winding or opto-isolator required for regulation n accurate en/uvlo threshold and hysteresis n internal compensation and soft-start n 5-lead tsot-23 package n isolated telecom, automotive, industrial, medical power supplies n isolated auxiliary/housekeeping power supplies efficiency vs load current LT8300 4:1 r fb sw 300h 19h en/uvlo 1m 2.2f 40.2k v in v in 36v to 72v v out + 5v 1ma to 300ma v out ? gnd 210k ? ? 47f 8300 ta01a load current (ma) efficiency (%) 100 20 30 90 40 10 60 70 80 50 0 8300 ta01b 300250200150100500 v in = 48v v in = 72v v in = 36v
LT8300 2 8300f p in c on f igura t ion a bsolu t e maxi m u m r a t ings sw (note 2) ........................................................... 150 v v in ......................................................................... 100 v en/uvlo ................................................................... v in r fb ...................................................... v in C 0.5v to v in current into r fb ................................................... 200 a operating junction temperature range (notes 3, 4) LT8300e, LT8300i ............................. C 40c to 125c LT8300h ............................................ C 40c to 150c LT8300mp ......................................... C 55c to 150c storage temperature range .................. C 65c to 150c (note 1) en/uvlo 1 gnd 2 top view s5 package 5-lead plastic tsot-23 r fb 3 5 v in 4 sw t jmax = 150c, ja = 150c/w o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range LT8300es5#pbf LT8300es5#trpbf ltgff 5-lead plastic tsot-23 C40c to 125c LT8300is5#pbf LT8300is5#trpbf ltgff 5-lead plastic tsot-23 C40c to 125c LT8300hs5#pbf LT8300hs5#trpbf ltgff 5-lead plastic tsot-23 C40c to 150c LT8300mps5#pbf LT8300mps5#trpbf ltgff 5-lead plastic tsot-23 C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LT8300 3 8300f e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the sw pin is rated to 150v for transients. depending on the leakage inductance voltage spike, operating waveforms of the sw pin should be derated to keep the flyback voltage spike below 150v as shown in figure 5. note 3: the LT8300e is guaranteed to meet performance specifications from 0c to 125c operating junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 24v, v en/uvlo = v in unless otherwise noted. symbol parameter conditions min typ max unit v in input voltage range 6 100 v v in uvlo threshold rising falling 5.8 3.2 6 v v i q v in quiescent current v en/uvlo = 0.3v v en/uvlo = 1.1v sleep mode (switch off) active mode (switch on) 1.2 200 70 330 2 a a a a en/uvlo shutdown threshold for lowest off i q l 0.3 0.75 v en/uvlo enable threshold falling hysteresis l 1.199 1.223 0.016 1.270 v v i hys en/uvlo hysteresis current v en/uvlo = 0.3v v en/uvlo = 1.1v v en/uvlo = 1.3v C0.1 2.2 C0.1 0 2.5 0 0.1 2.8 0.1 a a a f max maximum switching frequency 720 750 780 khz f min minimum switching frequency 6 7.5 9 khz t on(min) minimum switch-on time 160 ns t off(min) minimum switch-off time 350 ns t off(max) maximum switch-off time backup timer 200 s i sw(max) maximum sw current limit l 228 260 292 ma i sw(min) minimum sw current limit l 34 52 70 ma sw over current limit to initiate soft-start 520 ma r ds(on) switch on-resistance i sw = 100ma 10 i lkg switch leakage current v in = 100v, v sw = 150v 0.1 0.5 a i rfb r fb regulation current l 98 100 102 a r fb regulation current line regulation 6v v in 100v 0.001 0.01 %/v t ss soft-start timer 2.7 ms the LT8300i is guaranteed over the full C40c to 125c operating junction temperature range. the LT8300h is guaranteed over the full C40c to 150c operating junction temperature range. the LT8300mp is guaranteed over the full C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperature greater than 125c. note 4: the LT8300 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability.
LT8300 4 8300f typical p er f or m ance c harac t eris t ics boundary mode waveforms discontinuous mode waveforms burst mode waveforms v in shutdown current v in quiescent current, sleep mode v in quiescent current, active mode output load and line regulation output temperature variation switching frequency vs load current t a = 25c, unless otherwise noted. load current (ma) output voltage (v) 5.20 4.85 5.15 4.90 5.00 5.05 5.10 4.95 4.80 8300 g01 300250200150100500 v in = 36v v in = 48v v in = 72v front page application ambient temperature (c) output voltage (v) 5.5 4.6 5.4 4.7 5.0 5.1 5.2 5.3 4.8 4.9 4.5 8300 g02 150 7550 125100 250?25?50 front page application v in = 48v, i out = 200ma load current (ma) frequency (khz) 500 100 200 400 300 0 8300 g03 300250200150100500 front page application v in = 48v 2s/div front page application v in = 48v, i out = 300ma i lpri 100ma/div v sw 50v/div v out 50mv/div 8300 g04 2s/div front page application v in = 48v, i out = 60ma i lpri 100ma/div v sw 50v/div v out 50mv/div 8300 g05 20s/div front page application v in = 48v, i out = 1ma i lpri 100ma/div v sw 50v/div v out 50mv/div 8300 g06 v in (v) i q (a) 10 2 4 8 6 0 8300 g07 100 806040200 t j = ?55c t j = 150c t j = 25c v in (v) i q (a) 100 50 60 80 90 70 40 8300 g08 100 806040200 t j = 25c t j = ?55c t j = 150c v in (v) i q (a) 380 300 320 360 340 280 8300 g09 100 806040200 t j = 25c t j = ?55c t j = 150c
LT8300 5 8300f typical p er f or m ance c harac t eris t ics r ds(on) switch current limit maximum switching frequency minimum switching frequency minimum switch-on time minimum switch-off time en/uvlo enable threshold en/uvlo hysteresis current r fb regulation current t a = 25c, unless otherwise noted. temperature (c) v en/uvlo (v) 1.240 1.205 1.210 1.225 1.230 1.235 1.215 1.220 1.200 8300 g10 150 7550 125100 250?25?50 temperature (c) i hys (a) 5 1 2 3 4 0 8300 g11 150 7550 125100 250?25?50 temperature (c) i rfb (a) 105 101 102 103 104 100 96 97 98 99 95 8300 g12 150 7550 125100 250?25?50 temperature (c) resistance () 25 5 10 15 20 0 8300 g13 150 7550 125100 250?25?50 temperature (c) i sw (ma) 300 50 100 150 200 250 0 8300 g14 150 7550 125100 250?25?50 maximum current limit minimum current limit temperature (c) frequency (khz) 1000 200 400 600 800 0 8300 g15 150 7550 125100 250?25?50 temperature (c) frequency (khz) 20 4 8 12 16 0 8300 g16 150 7550 125100 250?25?50 temperature (c) time (ns) 400 100 200 300 0 8300 g17 150 7550 125100 250?25?50 temperature (c) time (ns) 400 100 200 300 0 8300 g18 150 7550 125100 250?25?50
LT8300 6 8300f p in func t ions en/uvlo (pin 1): enable/undervoltage lockout. the en/uvlo pin is used to enable the LT8300. pull the pin below 0.3v to shut down the LT8300. this pin has an ac - curate 1.223v threshold and can be used to program a v in undervoltage lockout (uvlo) threshold using a resistor divider from v in to ground. a 2.5a current hysteresis allows the programming of v in uvlo hysteresis. if neither function is used, tie this pin directly to v in . gnd (pin 2): ground. tie this pin directly to local ground plane. r fb (pin 3): input pin for external feedback resistor. connect a resistor from this pin to the transformer pri- mary sw pin. the ratio of the r fb resistor to the internal trimmed 12.23k resistor, times the internal bandgap reference, determines the output voltage (plus the effect of any non-unity transformer turns ratio). minimize trace area at this pin. sw (pin 4): drain of the 150v internal dmos power switch. minimize trace area at this pin to reduce emi and voltage spikes. v in (pin 5): input supply. the v in pin supplies current to internal circuitry and serves as a reference voltage for the feedback circuitry connected to the r fb pin. locally bypass this pin to ground with a capacitor.
LT8300 7 8300f b lock diagra m 8300 bd ? + ? + oscillator 1:4 s r q 1.223v 25a m2 m3 boundary detector driver ? + a2 a3 r sense 0.3 m1 g m r ref 12.23k r fb 2.5a r2 en/uvlo m4 3 4 5 ? + 1.223v a1 1 reference regulators v in 2 gnd r fb sw v in v in t1 n ps :1 d out l sec l pri v out + v out ? ? ? c out c in r1
LT8300 8 8300f o pera t ion the LT8300 is a current mode switching regulator ic de - signed specially for the isolated flyback topology. the key problem in isolated topologies is how to communicate the output voltage information from the isolated secondary side of the transformer to the primary side for regulation. historically, opto-isolators or extra transformer windings communicate this information across the isolation bound- ary. opto-isolator circuits waste output power, and the extra components increase the cost and physical size of the power supply. opto-isolators can also cause system issues due to limited dynamic response, nonlinearity, unit- to-unit variation and aging over lifetime. circuits employing extra transformer windings also exhibit deficiencies, as using an extra winding adds to the transformers physical size and cost, and dynamic response is often mediocre. the LT8300 samples the isolated output voltage through the primary-side flyback pulse waveform. in this manner, neither opto-isolator nor extra transformer winding is re- quired for regulation. since the LT8300 operates in either boundary conduction mode or discontinuous conduction mode, the output voltage is always sampled on the sw pin when the secondary current is zero. this method im - proves load regulation without the need of external load compensation components. the LT8300 is a simple to use micropower isolated flyback converter housed in a 5-lead tsot-23 package. the output voltage is programmed with a single external resistor. by integrating the loop compensation and soft-start inside, the part further reduces the number of external components. as shown in the block diagram, many of the blocks are similar to those found in traditional switching regulators including reference, regulators, oscillator, logic, current amplifier, current comparator, driver, and power switch. the novel sections include a flyback pulse sense circuit, a sample-and-hold error amplifier, and a boundary mode detector, as well as the additional logic for boundary conduction mode, discontinuous conduction mode, and low ripple burst mode operation. boundary conduction mode operation the LT8300 features boundary conduction mode operation at heavy load, where the chip turns on the primary power switch when the secondary current is zero. boundary conduction mode is a variable frequency, variable peak- current switching scheme. the power switch turns on and the transformer primary current increases until an internally controlled peak current limit. after the power switch turns off, the voltage on the sw pin rises to the output voltage multiplied by the primary-to-secondary transformer turns ratio plus the input voltage. when the secondary current through the output diode falls to zero, the sw pin voltage collapses and rings around v in . a boundary mode detector senses this event and turns the power switch back on. boundary conduction mode returns the secondary current to zero every cycle, so parasitic resistive voltage drops do not cause load regulation errors. boundary conduc - tion mode also allows the use of smaller transformers compared to continuous conduction mode and does not exhibit sub-harmonic oscillation. discontinuous conduction mode operation as the load gets lighter, boundary conduction mode in - creases the switching frequency and decreases the switch peak current at the same ratio. running at a higher switching frequency up to several mhz increases switching and gate charge losses. to avoid this scenario, the LT8300 has an additional internal oscillator, which clamps the maximum switching frequency to be less than 750khz. once the switching frequency hits the internal frequency clamp, the part starts to delay the switch turn-on and operates in discontinuous conduction mode. low ripple burst mode operation unlike traditional flyback converters, the LT8300 has to turn on and off at least for a minimum amount of time and with a minimum frequency to allow accurate sampling of the output voltage. the inherent minimum switch cur - rent limit and minimum switch-off time are necessary to guarantee the correct operation of specific applications. as the load gets very light, the LT8300 starts to fold back the switching frequency while keeping the minimum switch current limit. so the load current is able to decrease while still allowing minimum switch-off time for the sample- and-hold error amplifier. meanwhile, the part switches between sleep mode and active mode, thereby reducing the
LT8300 9 8300f o pera t ion effective quiescent current to improve light load efficiency. in this condition, the LT8300 operates in low ripple burst mode. the typical 7.5khz minimum switching frequency output voltage the r fb resistor as depicted in the block diagram is the only external resistor used to program the output voltage. the LT8300 operates similar to traditional current mode switchers, except in the use of a unique flyback pulse sense circuit and a sample-and-hold error amplifier, which sample and therefore regulate the isolated output voltage from the flyback pulse. operation is as follows: when the power switch m1 turns off, the sw pin voltage rises above the v in supply. the amplitude of the flyback pulse, i.e., the difference between the sw pin voltage and v in supply, is given as: v flbk = (v out + v f + i sec ? esr) ? n ps v f = output diode forward voltage i sec = transformer secondary current esr = total impedance of secondar y circuit n ps = transformer effective primary-to-secondary turns ratio the flyback voltage is then converted to a current i rfb by the flyback pulse sense circuit (m2 and m3). this cur - rent i rfb also flows through the internal trimmed 12.23k r ref resistor to generate a ground-referred voltage. the resulting voltage feeds to the inverting input of the sample- and-hold error amplifier. since the sample-and-hold error amplifier samples the voltage when the secondary current is zero, the (i sec ? esr) term in the v flbk equation can be assumed to be zero. the bandgap reference voltage v bg , 1.223v, feeds to the non-inverting input of the sample-and-hold error ampli- fier. the relatively high gain in the overall loop causes the voltage across r ref resistor to be nearly equal to the a pplica t ions i n f or m a t ion determines how often the output voltage is sampled and also the minimum load requirement. bandgap reference voltage v bg . the resulting relationship between v flbk and v bg can be expressed as: v flbk r fb ? ? ? ? ? ? ? r ref = v bg or v flbk = v bg r ref ? ? ? ? ? ? ? r fb = i rfb ? r fb v bg = bandgap reference voltage i rfb = r fb regulation current = 100a combination with the previous v flbk equation yields an equation for v out , in terms of the r fb resistor, transformer turns ratio, and diode forward voltage: v out = 100a ? r fb n ps ? ? ? ? ? ? ? v f output temperature coefficient the first term in the v out equation does not have tempera- ture dependence, but the output diode forward voltage v f has a significant negative temperature coefficient (C1mv/c to C2mv/c). such a negative temperature coefficient pro - duces approximately 200mv to 300mv voltage variation on the output voltage across temperature. for higher voltage outputs, such as 12v and 24v, the output diode temperature coefficient has a negligible effect on the output voltage regulation. for lower voltage outputs, such as 3.3v and 5v, however, the output diode temperature coefficient does count for an extra 2% to 5% output voltage regulation. for customers requiring tight output voltage regulation across temperature, please refer to other ltc parts with integrated temperature compensation features.
LT8300 10 8300f a pplica t ions i n f or m a t ion selecting actual r fb resistor value the LT8300 uses a unique sampling scheme to regulate the isolated output voltage. due to the sampling nature, the scheme contains repeatable delays and error sources, which will affect the output voltage and force a re-evaluation of the r fb resistor value. therefore, a simple two-step process is required to choose feedback resistor r fb . rearrangement of the expression for v out in the output voltage section yields the starting value for r fb : r fb = n ps ? v out + v f ( ) 100a v out = output voltage v f = output diode forward voltage = ~0.3v n ps = transformer effective primary-to-secondary turns ratio power up the application with the starting r fb value and other components connected, and measure the regulated output voltage, v out(meas) . the final r fb value can be adjusted to: r fb(final) = v out v out(meas) ? r fb once the final r fb value is selected, the regulation accuracy from board to board for a given application will be very consistent, typically under 5% when including device variation of all the components in the system (assuming resistor tolerances and transformer windings matching within 1%). however, if the transformer or the output diode is changed, or the layout is dramatically altered, there may be some change in v out . output power a flyback converter has a complicated relationship between the input and output currents compared to a buck or a boost converter. a boost converter has a relatively constant maximum input current regardless of input voltage and a buck converter has a relatively constant maximum output current regardless of input voltage. this is due to the continuous non-switching behavior of the two currents. a flyback converter has both discontinuous input and output currents which make it similar to a non-isolated buck-boost converter. the duty cycle will affect the input and output currents, making it hard to predict output power. in ad - dition, the winding ratio can be changed to multiply the output current at the expense of a higher switch voltage. the graphs in figures 1 to 4 show the typical maximum output power possible for the output voltages 3.3v, 5v, 12v, and 24v. the maximum output power curve is the calculated output power if the switch voltage is 120v dur - ing the switch-off time. 30v of margin is left for leakage inductance voltage spike. to achieve this power level at a given input, a winding ratio value must be calculated to stress the switch to 120v, resulting in some odd ratio values. the curves below the maximum output power curve are examples of common winding ratio values and the amount of output power at given input voltages. one design example would be a 5v output converter with a minimum input voltage of 36v and a maximum input voltage of 72v. a six-to-one winding ratio fits this design example perfectly and outputs equal to 2.44w at 72v but lowers to 1.87w at 36v. the following equations calculate output power: ? p out = ? v in ? d ? i sw(max) ? 0.5 = efficiency = ? 85% d = dutycycle = v out + v f ( ) ? n ps v out + v f ( ) ? n ps + v in i sw(max) = maximum switch current limit = 260ma
LT8300 11 8300f a pplica t ions i n f or m a t ion figure 4. output power for 24v output figure 1. output power for 3.3v output figure 2. output power for 5v output figure 3. output power for 12v output input voltage (v) 0 output power (w) 3.5 2.5 1.5 3.0 2.0 1.0 0.5 0 40 80 20 60 8300 f01 100 n = 12:1 maximum output power n = 8:1 n = 6:1 n = 4:1 input voltage (v) 0 output power (w) 3.5 2.5 1.5 3.0 2.0 1.0 0.5 0 40 80 20 60 8300 f02 100 maximum output power n = 2:1 n = 4:1 n = 6:1 n = 8:1 input voltage (v) 0 output power (w) 3.5 2.5 1.5 3.0 2.0 1.0 0.5 0 40 80 20 60 8300 f03 100 n = 4:1 maximum output power n = 3:1 n = 2:1 n = 1:1 input voltage (v) 0 output power (w) 3.5 2.5 1.5 3.0 2.0 1.0 0.5 0 40 80 20 60 8300 f04 100 n = 1:1 n = 3:2 n = 1:2 maximum output power n = 2:1 primary inductance requirement the LT8300 obtains output voltage information from the reflected output voltage on the sw pin. the conduction of secondary current reflects the output voltage on the primary sw pin. the sample-and-hold error amplifier needs a minimum 350ns to settle and sample the reflected output voltage. in order to ensure proper sampling, the second - ary winding needs to conduct current for a minimum of 350ns. the following equation gives the minimum value for primary-side magnetizing inductance: l pri t off(min) ? n ps ? v out + v f ( ) i sw(min) t off(min) = minimum switch-off time = 350ns i sw(min) = minimum switch current limit = 52ma in addition to the primary inductance requirement for the minimum switch-off time, the LT8300 has minimum switch-on time that prevents the chip from turning on the power switch shorter than approximately 160ns. this minimum switch-on time is mainly for leading-edge blank- ing the initial switch turn-on current spike. if the inductor current exceeds the desired current limit during that time, oscillation may occur at the output as the current control loop will lose its ability to regulate. therefore, the following equation relating to maximum input voltage must also be followed in selecting primary-side magnetizing inductance: l pri t on(min) ? v in(max) i sw(min) t on(min) = minimum switch-on time = 160ns
LT8300 12 8300f a pplica t ions i n f or m a t ion in general, choose a transformer with its primary mag - netizing inductance about 20% to 40% larger than the minimum values calculated above. a transformer with much larger inductance will have a bigger physical size and may cause instability at light load. selecting a transformer transformer specification and design is perhaps the most critical part of successfully applying the LT8300. in addition to the usual list of guidelines dealing with high frequency isolated power supply transformer design, the following information should be carefully considered. linear technology has worked with several leading mag - netic component manufacturers to produce pre-designed flyback transformers for use with the LT8300. table 1 shows the details of these transformers. turns ratio note that when choosing the r fb resistor to set output voltage, the user has relative freedom in selecting a trans - former turns ratio to suit a given application. in contrast, the use of simple ratios of small integers, e.g., 4:1, 2:1, 1:1, provides more freedom in settling total turns and mutual inductance. table 1. predesigned transformers typical specifications transformer part number l pri (h) l leakage (h) np:ns:nb vendor target applications 750312367 400 4.5 8:1 wrth elektronik 48v to 3.3v/0.51a, 24v to 3.3v/0.37a, 12v to 3.3v/0.24a 750312557 300 2.5 6:1 wrth elektronik 48v to 3.3v/0.42a, 24v to 3.3v/0.32a, 12v to 3.3v/0.22a 48v to 5v/0.38a, 24v to 5v/0.27a, 12v to 5v/0.17a 750312365 300 1.8 4:1 wrth elektronik 48v to 5v/0.29a, 24v to 5v/0.22a, 12v to 5v/0.15a 750312558 300 1.75 2:1:1 wrth elektronik 48v to 12v/67ma, 24v to 12v/50ma, 12v to 12v/33ma 48v to 15v/62ma, 24v to 15v/44ma, 12v to 15v/28ma 750312559 300 2 1:1 wrth elektronik 48v to 24v/67ma, 24v to 24v/50ma, 12v to 24v/33ma 750311019 400 5 6:1:2 wrth elektronik 48v to 3.3v/0.42a, 24v to 3.3v/0.32a, 12v to 3.3v/0.22a 48v to 5v/0.38a, 24v to 5v/0.27a, 12v to 5v/0.17a 750311558 300 1.5 4:1:1 wrth elektronik 48v to 5v/0.29a, 24v to 5v/0.22a, 12v to 5v/0.15a 750311660 350 3 2:1:0.33 wrth elektronik 48v to 12v/0.134a, 24v to 12v/0.1a, 12v to 12v/0.066a 48v to 15v/0.124a, 24v to 15v/0.088a, 12v to 15v/0.056a 750311838 350 3 2:1:1 wrth elektronik 48v to 12v/67ma, 24v to 12v/50ma, 12v to 12v/33ma 48v to 15v/62ma, 24v to 15v/44ma, 12v to 15v/28ma 750311659 300 2 1:1:0.2 wrth elektronik 48v to 24v/67ma, 24v to 24v/50ma, 12v to 24v/33ma 10396-t026 300 2.5 6:1:2 sumida 48v to 3.3v/0.42a, 24v to 3.3v/0.32a, 12v to 3.3v/0.22a 48v to 5v/0.38a, 24v to 5v/0.27a, 12v to 5v/0.17a 10396-t024 300 2 4:1:1 sumida 48v to 5v/0.29a, 24v to 5v/0.22a, 12v to 5v/0.15a 10396-t022 300 2 2:1:0.33 sumida 48v to 12v/0.134a, 24v to 12v/0.1a, 12v to 12v/0.066a 48v to 15v/0.124a, 24v to 15v/0.088a, 12v to 15v/0.056a 10396-t028 300 2.5 2:1:1 sumida 48v to 12v/67ma, 24v to 12v/50ma, 12v to 12v/33ma 48v to 15v/62ma, 24v to 15v/44ma, 12v to 15v/28ma l10-0116 500 7.3 6:1 bh electronics 48v to 3.3v/0.42a, 24v to 3.3v/0.32a, 12v to 3.3v/0.22a 48v to 5v/0.38a, 24v to 5v/0.27a, 12v to 5v/0.17a l10-0112 230 3.38 4:1 bh electronics 48v to 5v/0.29a, 24v to 5v/0.22a, 12v to 5v/0.15a l11-0067 230 2.16 4:1 bh electronics 48v to 5v/0.29a, 24v to 5v/0.22a, 12v to 5v/0.15a * all the transformers are rated for 1.5kv isolation.
LT8300 13 8300f typically, choose the transformer turns ratio to maximize available output power. for low output voltages (3.3v or 5v), a larger n:1 turns ratio can be used with multiple primary windings relative to the secondary to maximize the transformers current gain (and output power). however, remember that the sw pin sees a voltage that is equal to the maximum input supply voltage plus the output voltage multiplied by the turns ratio. in addition, leakage inductance will cause a voltage spike (v leakage ) on top of this reflected voltage. this total quantity needs to remain below the 150v absolute maximum rating of the sw pin to prevent breakdown of the internal power switch. to - gether these conditions place an upper limit on the turns ratio, n ps , for a given application. choose a turns ratio low enough to ensure: n ps < 150v ? v in(max) ? v leakage v out + v f for lower output power levels, choose a smaller n:1 turns ratio to alleviate the sw pin voltage stress. although a 1:n turns ratio makes it possible to have very high output voltages without exceeding the breakdown voltage of the internal power switch, the multiplied parasitic capacitance through turns ratio coupled with the relatively resistive 150v internal power switch may cause the switch turn-on current spike ringing beyond 160ns leading-edge blanking, thereby producing light load instability in certain applica- tions. so any 1:n turns ratio should be fully evaluated before its use with the LT8300. the turns ratio is an important element in the isolated feedback scheme, and directly affects the output voltage accuracy. make sure the transformer manufacturer speci - fies turns ratio accuracy within 1%. a pplica t ions i n f or m a t ion saturation current the current in the transformer windings should not exceed its rated saturation current. energy injected once the core is saturated will not be transferred to the secondary and will instead be dissipated in the core. when designing custom transformers to be used with the LT8300, the saturation current should always be specified by the transformer manufacturers. winding resistance resistance in either the primary or secondary windings will reduce overall power efficiency. good output voltage regulation will be maintained independent of winding re- sistance due to the boundary/discontinuous conduction mode operation of the LT8300. leakage inductance and snubbers transformer leakage inductance on either the primary or secondary causes a voltage spike to appear on the primary after the power switch turns off. this spike is increasingly prominent at higher load currents where more stored en - ergy must be dissipated. it is very important to minimize transformer leakage inductance. when designing an application, adequate margin should be kept for the worst-case leakage voltage spikes even under overload conditions. in most cases shown in figure 5, the reflected output voltage on the primary plus v in should be kept below 120v. this leaves at least 30v margin for the leakage spike across line and load conditions. a larger voltage margin will be required for poorly wound transformers or for excessive leakage inductance. in addition to the voltage spikes, the leakage inductance also causes the sw pin ringing for a while after the power switch turns off. to prevent the voltage ringing falsely trig - ger boundary mode detector, the LT8300 internally blanks the boundary mode detector for approximately 250ns. any remaining voltage ringing after 250ns may turn the power switch back on again before the secondary current falls to zero. so the leakage inductance spike ringing should be limited to less than 250ns.
LT8300 14 8300f a pplica t ions i n f or m a t ion a snubber circuit is recommended for most applications. two types of snubber circuits shown in figure 6 that can protect the internal power switch include the dz (diode- zener) snubber and the rc (resistor-capacitor) snubber. the dz snubber ensures well defined and consistent clamping voltage and has slightly higher power efficiency, while the rc snubber quickly damps the voltage spike ringing and provides better load regulation and emi performance. figure 5 shows the flyback waveforms with the dz and rc snubbers. for the dz snubber, proper care must be taken when choosing both the diode and the zener diode. schottky diodes are typically the best choice, but some pn diodes can be used if they turn on fast enough to limit the leak- age inductance spike. choose a diode that has a reverse- voltage rating higher than the maximum sw pin voltage. the zener diode breakdown voltage should be chosen to balance power loss and switch voltage protection. the best compromise is to choose the largest voltage breakdown. use the following equation to make the proper choice: v zener(max) 150v C v in(max) for an application with a maximum input voltage of 72v, choose a 68v zener diode, the v zener(max) of which is around 72v and below the 78v maximum. the power loss in the clamp will determine the power rat - ing of the zener diode. power loss in the clamp is highest at maximum load and minimum input voltage. the switch current is highest at this point along with the energy stored in the leakage inductance. a 0.5w zener will satisfy most applications when the highest v zener is chosen. figure 5. maximum voltages for sw pin flyback waveform figure 6. snubber circuits 8300 f05 v sw t off > 350ns v leakage t sp < 250ns v sw v sw time no snubber with dz snubber with rc snubber t off > 350ns v leakage t sp < 250ns time t off > 350ns v leakage t sp < 250ns time <150v <120v <150v <120v <150v <120v 8300 f06b 8300 f06a dz snubber rc snubber l ? z d c r ? ? l ? ? ?
LT8300 15 8300f a pplica t ions i n f or m a t ion tables 2 and 3 show some recommended diodes and zener diodes. table 2. recommended zener diodes part v zener (v) power (w) case vendor mmsz5266bt1g 68 0.5 sod-123 on semi mmsz5270bt1g 91 0.5 sod-123 cmhz5266b 68 0.5 sod-123 central semiconductor cmhz5267b 75 0.5 sod-123 bzx84j-68 68 0.5 sod323f nxp bzx100a 100 0.5 sod323f table 3. recommended diodes part i (a) v reverse (v) case vendor bav21w 0.625 200 sod-123 diodes inc. bav20w 0.625 150 sod-123 the recommended approach for designing an rc snubber is to measure the period of the ringing on the sw pin when the power switch turns off without the snubber and then add capacitance (starting with 100pf) until the period of the ringing is 1.5 to 2 times longer. the change in period will determine the value of the parasitic capacitance, from which the parasitic inductance can be determined from the initial period, as well. once the value of the sw node capacitance and inductance is known, a series resistor can be added to the snubber capacitance to dissipate power and critically dampen the ringing. the equation for deriving the optimal series resistance using the observed periods ( t period and t period(snubbed) ) and snubber capacitance (c snubber ) is: c par = c snubber t period(snubbed) t period ? ? ? ? ? ? 2 ? 1 l par = t period 2 c par ? 4 2 r snubber = l par c par figure 7. undervoltage lockout (uvlo) LT8300 gnd en/uvlo r1 run/stop control (optional) r2 v in 8300 f07 note that energy absorbed by the rc snubber will be converted to heat and will not be delivered to the load. in high voltage or high current applications, the snubber may need to be sized for thermal dissipation. undervoltage lockout (uvlo) a resistive divider from v in to the en/uvlo pin imple- ments undervoltage lockout (uvlo). the en/uvlo pin falling threshold is set at 1.223v with 16mv hysteresis. in addition, the en/uvlo pin sinks 2.5a when the volt- age at the pin is below 1.223v. this current provides user programmable hysteresis based on the value of r1. the programmable uvlo thresholds are: v in(uvlo + ) = 1.239v ? (r1 + r2) r2 + 2.5a ? r1 v in(uvlo ? ) = 1.223v ? (r1 + r2) r2 figure 7 shows the implementation of external shutdown control while still using the uvlo function. the nmos grounds the en/uvlo pin when turned on, and puts the LT8300 in shutdown with quiescent current less than 2a.
LT8300 16 8300f minimum load requirement the LT8300 samples the isolated output voltage from the primary-side flyback pulse waveform. the flyback pulse occurs once the primary switch turns off and the secondary winding conducts current. in order to sample the output voltage, the LT8300 has to turn on and off at least for a minimum amount of time and with a minimum frequency. the LT8300 delivers a minimum amount of energy even during light load conditions to ensure accurate output volt- age information. the minimum energy delivery creates a minimum load requirement, which can be approximately estimated as: i load(min) = l pri ? i sw(min) 2 ? f min 2 ? v out l pri = transformer primary inductance i sw(min) = minimum switch current limit = 52ma f min = minimum switching frequency = 7.5khz the LT8300 typically needs less than 0.5% of its full output power as minimum load. alternatively, a zener diode with its breakdown of 20% higher than the output voltage can serve as a minimum load if pre-loading is not acceptable. for a 5v output, use a 6v zener with cathode connected to the output. output short protection when the output is heavily overloaded or shorted, the reflected sw pin waveform rings longer than the internal blanking time. after the 350ns minimum switch-off time, the excessive ring falsely trigger the boundary mode detector and turn the power switch back on again before the secondary current falls to zero. under this condition, the LT8300 runs into continuous conduction mode at 750khz maximum switching frequency. depending on the v in supply voltage, the switch current may run away and exceed 260ma maximum current limit. once the switch current hits 520ma over current limit, a soft-start cycle initiates and throttles back both switch current limit and switch frequency. this output short protection prevents the switch current from running away and limits the average output diode current. a pplica t ions i n f or m a t ion design example use the following design example as a guide to design applications for the LT8300. the design example involves designing a 12v output with a 120ma load current and an input range from 36v to 72v. v in(min) = 36v, v in(nom) = 48v, v in(max) = 72v, v out = 12v, i out = 120ma step 1: select the transformer turns ratio. n ps < 150v ? v in(max) ? v leakage v out + v f v leakage = margin for transformer leakage spike = 30v v f = output diode forward voltage = ~0.3v example: n ps < 150v ? 72v ? 30v 12v + 0.3v = 3.9 the choice of transformer turns ratio is critical in deter - mining output current capability of the converter. table 4 shows the switch voltage stress and output current capa- bility at different transformer turns ratio. table 4. switch voltage stress and output current capability vs turns ratio n ps v sw(max) at v in(max) (v) i out(max) at v in(min) (ma) duty cycle (%) 1:1 84.3 84 15-25 2:1 96.6 135 25-41 3:1 108.9 168 34-51 since both n ps = 2 and n ps = 3 can meet the 120ma output current requirement, n ps = 2 is chosen in this example to allow more margin for transformer leakage inductance voltage spike.
LT8300 17 8300f a pplica t ions i n f or m a t ion step 2: determine the primary inductance. primary inductance for the transformer must be set above a minimum value to satisfy the minimum switch-off and switch-on time requirements: l pri t off(min) ? n ps ? v out + v f ( ) i sw(min) l pri t on(min) ? v in(max) i sw(min) t off(min) = 350ns t on(min) = 160ns i sw(min) = 52ma example: l pri 350ns ? 2 ? (12v + 0.3v) 52ma = 166h l pri 160ns ? 72v 52ma = 222h most transformers specify primary inductance with a toler - ance of 20%. with other component tolerance considered, choose a transformer with its primary inductance 20% to 40% larger than the minimum values calculated above. l pri = 300h is then chosen in this example. once the primary inductance has been determined, the maximum load switching frequency can be calculated as: f sw = 1 t on + t off = 1 l pri ? i sw v in + l pri ? i sw n ps ? (v out + v f ) i sw = v out ? i out ? 2 ? v in ? d example: d = (12v + 0.3v) ? 2 (12v + 0.3v) ? 2 + 48v = 0.34 i sw = 12v ? 0.12a ? 2 0.85 ? 48v ? 0.34 = 0.21a f sw = 260khz the transformer also needs to be rated for the correct saturation current level across line and load conditions. a saturation current rating larger than 400ma is necessary to work with the LT8300. the 10396-t022 from sumida is chosen as the flyback transformer. step 3: choose the output diode. two main criteria for choosing the output diode include forward current rating and reverse voltage rating. the maximum load requirement is a good first-order guess as the average current requirement for the output diode. a conservative metric is the maximum switch current limit multiplied by the turns ratio, i diode(max) = i sw(max) ? n ps example: i diode(max) = 0.52a next calculate reverse voltage requirement using maxi- mum v in : v reverse = v out + v in(max) n ps example: v reverse = 12v + 72v 2 = 48v the sbr0560s1 (0.5a, 60v diode) from diodes inc. is chosen.
LT8300 18 8300f step 4: choose the output capacitor. the output capacitor should be chosen to minimize the output voltage ripple while considering the increase in size and cost of a larger capacitor. use the equation below to calculate the output capacitance: c out = l pri ? i sw 2 2 ? v out ? ? v out example: design for output voltage ripple less than 1% of v out , i.e., 120mv. c out = 300h ? (0.21a) 2 2 ? 12v ? 0.12v = 4.6f remember ceramic capacitors lose capacitance with ap- plied voltage. the capacitance can drop to 40% of quoted capacitance at the maximum voltage rating. so a 10uf, 16v rating ceramic capacitor is chosen. step 5: design snubber circuit. the snubber circuit protects the power switch from leakage inductance voltage spike. a dz snubber is recommended for this application because of lower leakage inductance and larger voltage margin. the zener and the diode need to be selected. the maximum zener breakdown voltage is set according to the maximum v in : v zener(max) 150v C v in(max) example: v zener(max) 150v C 72v = 78v a pplica t ions i n f or m a t ion a 68v zener with a maximum of 72v will provide optimal protection and minimize power loss. so a 68v, 0.5w zener from on semiconductor (mmsz5266bt1g) is chosen. choose a diode that is fast and has sufficient reverse voltage breakdown: v reverse > v sw(max) v sw(max) = v in(max) + v zener(max) example: v reverse > 144v a 150v, 0.6a diode from diodes inc. (bav20w) is chosen. step 6: select the r fb resistor. use the following equation to calculate the starting value for r fb : r fb = n ps ? (v out + v f ) 100a example: r fb = 2 ? (12v + 0.3v) 100a = 246k depending on the tolerance of standard resistor values, the precise resistor value may not exist. for 1% standard values, a 243k resistor in series with a 3.01k resistor should be close enough. as discussed in the application information section, the final r fb value should be adjusted on the measured output voltage.
LT8300 19 8300f a pplica t ions i n f or m a t ion step 7: select the en/uvlo resistors. determine the amount of hysteresis required and calculate r1 resistor value: v in(hys) = 2.5a ? r1 example: choose 2.5v of hysteresis, r1 = 1m determine the uvlo thresholds and calculate r2 resistor value: v in(uvlo + ) = 1.239v ? (r1 + r2) r2 + 2.5a ? r1 example: set v in uvlo rising threshold to 34.5v, r2 = 40.2k v in(uvlo+) = 34.1v v in(uvloC) = 31.6v step 8: ensure minimum load. the theoretical minimum load can be approximately estimated as: i load(min) = 300h ? (52ma) 2 ? 7.5khz 2 ? 12v = 0.25ma remember to check the minimum load requirement in real application. the minimum load occurs at the point where the output voltage begins to climb up as the converter delivers more energy than what is consumed at the out- put. the real minimum load for this application is about 0.6ma, 0.5% of 120ma maximum load. in this example, a 20k resistor is selected as the minimum load.
LT8300 20 8300f typical a pplica t ions LT8300 t1 6:1 d1 r fb sw 300h 8h en/uvlo 1m 2.2f 40.2k v in v in 36v to 72v v out + 5v 1ma to 330ma v out ? gnd 316k t1: wrth 750312557 d1: diodes inc. sbr2a30p1 ? ? 47f 8300 ta02 5v micropower isolated flyback converter 12v micropower isolated flyback converter LT8300 t1 2:1 d1 r fb sw 300h 75h en/uvlo 1m 2.2f 40.2k v in v in 36v to 72v v out + 12v 0.6ma to 120ma v out ? gnd 243k t1: sumida 10396-to22 d1: diodes inc. sbr0560s1 ? ? 10f 8300 ta03
LT8300 21 8300f typical a pplica t ions LT8300 t1 8:1 d1 r fb sw 400h 6h en/uvlo 1m 2.2f 40.2k v in v in 36v to 72v v out + 3.3v 2ma to 440ma v out ? gnd 287k t1: wrth 750312367 d1: nxp pmeg2020eh ? ? 100f 8300 ta05 24v micropower isolated flyback converter 3.3v micropower isolated flyback converter LT8300 t1 1:1 d1 r fb sw 300h 300h en/uvlo 1m 2.2f 40.2k v in v in 36v to 72v v out + 24v 0.3ma to 60ma v out ? gnd 243k t1: wrth 750311559 d1: diodes dfls 1200-7 ? ? 4.7f 8300 ta04
LT8300 22 8300f typical a pplica t ions v in to (v in + 10v) micropower converter v in to (v in C 10v) micropower converter LT8300 d1 z1 r fb sw l1 330h en/uvlo 1m 1f 118k v in v in 15v to 80v v out + 10v 100ma v out ? gnd 102k l1: coiltronics dr73-331-r d1: diodes inc. sbr1u150sa z1: central cmdz12l 8300 ta07 4.7f LT8300 d1 z1 r fb sw l1 330h en/uvlo 1m 1f 118k v in v in 15v to 80v v out + 10v 50ma v out ? gnd 102k l1: coiltronics dr73-331-r d1: diodes inc. sbr1u150sa z1: central cmdz12l 8300 ta06 4.7f
LT8300 23 8300f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion s5 package 5-lead plastic tsot-23 (reference ltc dwg # 05-08-1635 rev b) 1.50 ? 1.75 (note 4) 2.80 bsc 0.30 ? 0.45 typ 5 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) s5 tsot-23 0302 rev b pin one 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LT8300 24 8300f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0812 ? printed in usa r ela t e d p ar t s typical a pplica t ion 3.3v isolated converter (conforming to def-stan61-5) part number description comments lt3511/lt3512 100v isolated flyback converters monolithic no-opto flybacks with integrated 240ma/420ma switch, msop-16(12) lt3748 100v isolated flyback controller 5v v in 100v, no opto flyback , msop-16 with high voltage spacing lt3798 off-line isolated no opto-coupler flyback controller with active pfc v in and v out limited only by external components lt3573/lt3574/lt3575 40v isolated flyback converters monolithic no-opto flybacks with integrated 1.25a/0.65a/2.5a switch lt3757/lt3759/lt3758 40v/100v flyback/boost controllers universal controllers with small package and powerful gate drive lt3957/lt3958 40v/100v flyback/boost converters monolithic with integrated 5a/3.3a switch ltc3803/ltc3803-3/ ltc3803-5 200khz/300khz flyback controllers in sot-23 v in and v out limited by external components ltc3805/ltc3805-5 adjustable frequency flyback controllers v in and v out limited by external components v in (v) i vin (a) 400 200 300 100 0 8300 ta08b 3230282624 20 22 18 LT8300 l1 1:1 d1 r fb sw 150h 150h en/uvlo 1m 1f 93.1k v in v in 18v to 32v v out + 3.3v 0ma to 20ma v out ? gnd 42.2k d1: diodes inc. sbr0560s1-7 l1: drq73-151-r z1: central cmdz4l7 ? ? 1f 1f z1 8300 ta08a lt3009-3.3 gnd shdn in out input current with no load

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